The present invention relates to semiconductor integrated circuit devices, and more particularly to semiconductor integrated circuit devices in which insulated gate type field effect transistors (hereinafter referred to as MOSFET's) are formed in relatively small sizes to realize a high degree of integration.
Generally, a semiconductor integrated circuit device includes a plurality of elements (such as MOSFET's) which may be provided in a semiconductor substrate with isolation regions formed among these elements. In the prior art, the isolation region comprises a thick field insulating film partially buried in the semiconductor substrate, and a channel stopper region formed beneath the field insulating film. The channel stopper region has the same conductivity type that the semiconductor substrate has and an impurity concentration which is higher than the impurity concentration of the substrate. The isolation region works to effectively isolate the individual elements from each other even where a wiring layer with a channel-forming voltage runs on the field insulating film.
Recently, circuit elements in the semiconductor integrated circuit device become progressively smaller in size to provide a higher degree of integration. In this case, it is necessary to reduce the size in three dimensions, i.e., to reduce the size in the vertical direction as well as in the lateral direction.
When the field insulating film is formed, its end appears in the active region to some extent depending upon the thickness of the film to form a so-called "bird's beak". In the case of a large element, i.e., where the element has a large active region as in the conventional art, the biting amount may be negligible. However, where the element is to be formed in a small size, the bird's beak becomes a serious problem. Therefore, the thickness of the field insulating film must be reduced to decrease the amount of biting. For the purpose of enchancing the integration density, the width of the wiring layer must also be reduced from, for example, 3 to 4 .mu.m to about 1 .mu.m in order to reduce the planar area.
In this case, the thickness of the wiring layer must also be reduced because of its side etching phenomenon, and the like, in the patterning process. The wiring layer having the reduced thickness is apt to break off at a step portion between the surface of the substrate and the upper surface of the field insulating film. Therefore, the thickness of the field insulating film cannot be made very large. From the viewpoint of a manufacturing process, an aligning of the mask with a high precision is essential for effecting fine patterning. For this purpose, the surface of the semiconductor substrate must be as flat as possible. That is, as the size is reduced in a planar shape, the size must also be reduced in a three dimensional shape, to obtain a substantially flat surface.
In view of these requirements, the thickness of the field insulating film must be reduced in the isolation regions among the elements. Here, there is a problem since the isolation of the elements decreases, i.e., a threshold voltage V.sub.th in the field region decreases. However, this problem can be solved if the concentration of the channel stopper region is increased. According to the conventional art, however, a remaining unsolved problem is that of parasitic capacity which occurs between the wiring layer provided on the field insulating film and the semiconductor substrate. That is, if an attempt is made to reduce the thickness of the field insulating film in order to reduce the size, the parasitic capacity tends to increase because of the reduced thickness of the field insulating film. Moreover, if the impurity concentration of the channel stopper region is increased to prevent the threshold voltage from being decreased, the parasitic capacity increases further. This fact seriously hinders the semiconductor device from operating at a high speed.